The present invention relates generally to a phase change memory device, and more particularly to a technology of verifying an operating condition corresponding to a characteristic of each phase change resistance cell included in a cell array in a write mode so as to write a reset data normally.
A nonvolatile memory has a data processing speed similar to that of a volatile Random Access Memory (RAM), however, unlike a volatile RAM, a nonvolatile memory conserves data even when no power is supplied to the memory, that is, after the power is turned off.
FIGS. 1a and 1b are diagrams showing a conventional phase change resistor (PCR) 4.
The PCR 4 comprises a phase change material (PCM) 2 inserted between an upper electrode 1 and a lower electrode 3. When a voltage and a current are applied to the PCR 4, a high temperature is generated in the PCM 2 such that an electric conductive state of the PCR 4 is changed depending on resistance.
The PCM comprises AgLnSbTe. The PCM 2 may also comprise chalcogenide having chalcogen elements (S, Se, Te) as a main ingredient, specifically a germanium antimonic tellurium (Ge2Sb2Te5) consisting of Ge—Sb—Te.
FIGS. 2a and 2b are diagrams showing the principle operation of the conventional PCR 4.
As shown in FIG. 2a, the PCM 2 can be crystallized when a low current, i.e., a current of less than a threshold value, flows through the PCR 4. As a result, the PCM 2 becomes a crystallized low resistance material.
As shown in FIG. 2b, the PCM 2 can be amorphized when a high current, i.e., a current higher than a threshold value, flows through the PCR 4. That is, the temperature of the PCM 3 is increased higher that its melting point when a high current flows through the PCR 4. As a result, the PCM 2 becomes an amorphous high resistance material.
In this way, the PCR 4 is configured to store nonvolatile data corresponding to the two resistance states. Data “1” refers to the PCR 4 having a low resistance state, and data “0” refers to the PCR 4 having a high resistance state so that the logic states of the two data can be stored.
FIG. 3 is a diagram showing a write operation of a conventional phase change resistant cell.
Heat is generated when a current flows through the upper electrode 1 and the lower electrode 3 of the PCR 4 for a given time. As a result, a state of the PCM 2 is changed to be either crystalline or amorphous depending on temperature given to the upper electrode 1 and the lower electrode 3.
When a low current flows for a given time, the PCM 2 becomes crystalline and the PCR 4, having a low resistance, is at a set state. On the other hand, when a high current flows for a given time, the PCM becomes amorphous and the PCR 4, having a high resistance, is at a reset state. The difference between two phases corresponds to a change in electric resistance.
As shown in FIG. 3, a low voltage is applied to the PCR 4 for a period of time in order to write the set state in a write mode. On the other hand, a high voltage is applied to the PCR 4 for a shorter period of time in order to write the reset state in the write mode.
FIG. 4 is a diagram showing a cell array of a conventional phase change memory device.
The conventional cell array as shown in FIG. 4 includes a plurality of bit lines BL0˜BL3 arranged in a column direction and a plurality of word lines WL0˜WL3 arranged in a row direction. The cell array also includes unit change resistance cells C positioned at intersections of the bit lines BL0˜BL3 and the word lines WL0˜WL3. The unit phase change resistance cell C includes a phase change resistor PCR and a PN diode D.
The phase change resistor PCR has a first terminal connected to the bit line BL and a second terminal connected to a P-type region of the PN diode D. The P-type region of the PN diode D is connected to the second terminal of the phase change resistor PCR and the N-type region of the PN diode D is connected to the word line WL.
In the cell array of the conventional phase change memory device, the phase of the phase change resistor PCR is varied depending on a set current Iset and a reset current Ireset flowing through each bit line BL to a write data.
A sense amplifier S/A senses cell data received through the bit line BL and compares the cell data with a reference voltage ref to distinguish set data from reset data. A reference current Iref flows in a reference voltage ref receiving terminal. A write driving unit W/D supplies a driving voltage, which corresponds to a data state, to the bit line BL when data is written in the unit phase change resistance cell C.
FIG. 5 is a flow chart showing a write cycle operation of a conventional phase change memory device.
When the write cycle begins, a new write operation begins regardless of the data stored in the unit phase change resistance cell C. For example, even when the data stored in the phase change resistance cell C is identical with the data to be written, a new write operation is performed. As a result, the number of write operations of the reset data and a set data is increased thereby increasing power consumption, and the cell is degraded to deteriorate a write characteristic.
FIG. 6 is a diagram showing the read current relationship of a conventional phase change memory device.
Each phase change resistance cell C included in a cell array has a different read current distribution depending on process, device and design conditions. That is, the distribution of the set current Iset, which corresponds to the set data, and the reset current Ireset, which corresponds to the reset data, becomes broader based on a read current.
As a result, the read currents of some cells may be overlap the read currents of other cells based on the reference current Iref. When the reset current Ireset is distinguished from the set current Iset by the reference current Iref, a data fail is generated in the unit phase change resistance cell C.